The next generation of high performance computing (HPC) fabrics use Intel® Omni-Path Architecture to create fabrics that meet the needs of the most demanding set of applications. The Intel® Omni-Path Edge Switch consists of two models supporting 100 Gb/s for all ports, an entry-level 24-port switch for small clusters and a 48-port switch.
The larger switch, in addition to enabling a 48-port fabric in 1U, can be combined with other edge switches and directors to build much larger multitier fabrics. These Intel Omni-Path Edge Switches are members of the Intel® Omni-Path Fabric 100 series of switches, host adapters, and software delivering an exceptional set of high-speed networking features and functions.
Intel® Omni-Path Architecture Switch Fabric Optimizations
While similar to existing technology, Intel® Omni-Path Architecture has been enhanced to overcome the scaling challenges of large-sized clusters.
These enhancements include:
High Message Rate Throughput. Intel Omni-Path Architecture is designed to support high message rate traffic from each node through the fabric. With ever-increasing processing power and core counts in Intel® Xeon® and Intel® Xeon Phi™ processors, that means the fabric has to support high bandwidth as well as high message rate throughput.
48-port Switch ASIC. Intel OPA switch 48-port design provides for improved fabric scalability, reduced latency, increased density, and reduced cost and power. In fact, the 48-port ASIC can enable 5 hop configurations of up to 27,648 nodes, or over 2.3x what’s possible with current InfiniBand* solutions. Depending on fabric size, this can reduce fabric infrastructure requirements in a typical fat tree configuration by over 50 percent, since fewer switches, cables, racks, and power are needed as compared to today’s 36-port switch ASICs. Table 1 summarizes the Intel OPA advantages.
Deterministic Latency. Features in Intel OPA will help minimize the negative performance impacts of large Maximum Transfer Units (MTUs) on small messages and help maintain consistent latency for interprocess communication (IPC) messages, such as Message Passing Interface (MPI) messages, when large messages—typically storage—are being simultaneously transmitted in the fabric. This will allow Intel OPA to bypass lower priority large packets to allow higher priority small packets, creating a low and more predictable latency through the fabric.
Enhanced End-to-End Reliability. Intel Omni-Path Architecture will also deliver efficient detection and error correction, which is expected to be much more efficient then forward error correction (FEC) defined in the InfiniBand standard. Enhancements include zero load for detection, and if a correction is required, packets only need to be retransmitted from the last link—not all the way from the sending node—which enables near zero additional latency for a correction.
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